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| 2N6796 Data Sheet November 1998 File Number 1594.2 8A, 100V, 0.180 Ohm, N-Channel Power MOSFET The 2N6796 is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Features * 8A, 100V * rDS(ON) = 0.180 * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Majority Carrier Device Ordering Information PART NUMBER 2N6796 PACKAGE TO-205AF BRAND 2N6796 * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" NOTE: When ordering, use the entire part number. Symbol D G S Packaging JEDEC TO-205AF DRAIN (CASE) SOURCE GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 321-724-7143 | Copyright (c) Intersil Corporation 1999 2N6796 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified 2N6796 100 100 8 5 32 20 8 32 25 0.20 -55 to 150 300 260 UNITS V V A A A V A A W W/oC oC oC oC Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IS Pulse Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS VDS(ON) IGSS rDS(ON) VSD gfs td(ON) tr td(OFF) tf CISS COSS CRSS RJC RJA SOA Free Air Operation VDS = 80V, ID = 310mA VDS = 3.12V, ID = 8A VDS = 25V, VGS = 0V, f = 1MHz, (Figure 11) TEST CONDITIONS ID = 0.25mA, VGS = 0V VGS = VDS, ID = 0.5mA VDS = 100V, VGS = 0V VDS = 80V, VGS = 0V, TC = 125oC ID = 8A, VGS = 10V VGS = 20V ID = 5A, VGS = 10V ID = 5A, VGS = 10V, TC = 125oC TC = 25oC, IS = 8A, VGS = 0V VDS = 5V, ID = 5A VDD 30V, ID = 5A, RG = 50 (Figure 17) MOSFET Switching Times are Essentially Independent of Operating Temperature MIN 100 2 0.75 3 350 150 50 25 25 TYP 0.14 5.5 600 300 100 MAX 4 250 1000 1.56 100 0.180 0.350 1.5 9 30 75 40 45 900 500 150 5 175 UNITS V V A A V nA V S ns ns ns ns pF pF pF oC/W oC/W Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Diode Forward Voltage (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Safe Operating Area W W Source to Drain Diode Specifications PARAMETER Reverse Recovery Time Reverse Recovered Charge NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). SYMBOL trr QRR TEST CONDITIONS TJ = 150oC, ISD = 8A, dISD/dt = 100A/s TJ = 150oC, ISD = 8A, dISD/dt = 100A/s MIN TYP 300 1.5 MAX UNITS ns C 2 2N6796 Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 ID, DRAIN CURRENT (A) Unless Otherwise Specified 10 8 6 0.6 0.4 4 0.2 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 2 0 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 ZJC, NORMALIZED THERMAL IMPEDANCE 0.5 0.2 PDM 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 1 10 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) ID, DRAIN CURRENT (A) 10s 100s 1ms ID, DRAIN CURRENT (A) 35 10V 30 25 8V 20 15 10 5 0 1000 7V 6V 5V 4V 0 10 20 30 40 50 9V PULSE DURATION = 80s 10 1 TC = 25oC TJ = MAX RATED SINGLE PULSE 10ms 100ms DC -0.1 -1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 3 2N6796 Typical Performance Curves 35 30 ID, DRAIN CURRENT (A) 25 20 15 10 5 0 0 1 9V 8V 7V 6V 5V 4V 4 2 3 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 6 Unless Otherwise Specified (Continued) PULSE DURATION = 80s VGS = 10V ID, DRAIN CURRENT (A) 35 80s PULSE TEST 30 25 20 15 10 5 0 TJ = 125oC TJ = 25oC TJ = -55oC 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 6. SATURATION CHARACTERISTICS 0.6 rDS(ON), ON-STATE RESISTANCE () 0.5 0.4 0.3 0.2 VGS = 20V 0.1 0 NORMALIZED ON-RESISTANCE 2.00 1.75 1.50 1.25 1.00 0.75 0.50 FIGURE 7. TRANSFER CHARACTERISTICS VGS = 10V ID = 4A VGS = 10V 0 10 20 30 40 ID, DRAIN CURRENT (A) 50 60 0.25 -80 -40 80 120 0 40 TJ , JUNCTION TEMPERATURE (oC) 160 NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.15 NORMALIZED ON-RESISTANCE 1.10 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 1600 1.05 1.00 0.95 0.90 0.85 0.80 -80 0 -40 80 120 0 40 TJ , JUNCTION TEMPERATURE (oC) 160 C, CAPACITANCE (pF) 1200 800 CISS 400 COSS CRSS 0 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 4 2N6796 Typical Performance Curves 10 gfs, TRANSCONDUCTANCE (S) Unless Otherwise Specified (Continued) ISD, SOURCE TO DRAIN CURRENT (A) 80s PULSE TEST 5 8 TJ = -55oC TJ = 25oC TJ = 125oC 2 10 5 6 4 TJ = 150oC TJ = 25oC 2 2 1 0 0 5 10 15 20 25 ID, DRAIN CURRENT (A) 30 35 0 0.5 1.0 1.5 2.0 2.5 VSD, SOURCE TO DRAIN VOLTAGE (V) 3.0 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 ID = 18A VGS, GATE TO SOURCE (V) VDS = 20V VDS = 50V VDS = 80V 15 10 5 0 0 8 16 24 Qg , TOTAL GATE CHARGE (nC) 32 FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 2N6796 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS 90% tOFF td(OFF) tf 90% + RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2F 50k 0.3F G DUT 0 IG(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR IG(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 6 2N6796 TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE OD OD1 A P INCHES SYMBOL A Ob MIN 0.160 0.016 0.350 0.315 0.095 0.190 0.095 0.010 0.028 0.029 0.500 0.075 MAX 0.180 0.021 0.370 0.335 0.105 0.210 0.105 0.020 0.034 0.045 0.560 - MILLIMETERS MIN 4.07 0.41 8.89 8.01 2.42 4.83 2.42 0.26 0.72 0.74 12.70 1.91 MAX 4.57 0.53 9.39 8.50 2.66 5.33 2.66 0.50 0.86 1.14 14.22 NOTES 2, 3 4 4 4 3 5 h L SEATING PLANE Ob OD OD1 e e1 e e1 90o 3 e2 h j k L P k 2 e2 45o j 1 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 7 |
Price & Availability of 2N6796
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